1. Field of Invention
The present invention relates in general to the data processing field. More particularly, the present invention relates to a method, apparatus and computer program product for spacing periodic commands (e.g., refresh commands, ZQ calibration commands, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision.
2. Background Art
The charge in each memory cell of a dynamic random access memory (DRAM) and other types of volatile memory has a natural tendency to degrade into a lower energy-state. Consequently, such memory cells require periodic charge “refreshing” to maintain stored data.
When accessing any type of volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) that requires periodic refreshes of ranks or banks, it is difficult to adequately control when the refresh commands happen. Generally, there is a timer that expires when the refresh command must be sent to the corresponding memory. If there are multiple ranks and/or banks that require refreshes, the refresh commands tend to bunch together. This tendency to bunch together also occurs with respect to other periodic commands, such as ZQ calibration commands (i.e., the ZQ calibration short (ZQCS) command and/or the ZQ calibration long (ZQCL) command).
Typically, the problem of periodic commands bunching together is ignored. Ignoring the problem, however, is not without cost. In the case of refresh commands, for example, if there are many refreshes waiting to be sent to the memory by a memory controller, the memory controller can get bogged down and efficiency can decrease rapidly as the refreshes plug up the command flow. Performance of a given memory can drop to such an extent that there must be enhancements made. One of these enhancements is changing the arbitration of refreshes so they are a higher priority to be executed than other commands. This enhancement, however, can make matters worse as far as slowing down performance by not allowing Reads and Writes to flow.
It is known to stagger refresh commands for the purpose of solving a different problem, i.e., simultaneous refreshes can cause severe power supply glitches. For example, U.S. Pat. No. 4,887,240 to Garverick et al. teaches each successive refresh to multiple banks of a DRAM array is staggered by one clock period. This staggered refresh technique is employed in the Garverick et al. patent to avoid large power supply current spikes while minimizing the effect on memory access bandwidth. U.S. Patent Application Publication No. 2008/0109598 A1 to Schakel et al. discloses a method and apparatus for refresh management of memory modules. The Schakel et al. reference teaches that it is desirable to manage the application of refresh operations such that current draw and voltage levels remain within acceptable limits by generating staggered refresh commands. While staggering refresh commands solves the power supply glitch problem, staggering the refresh commands so that they occur at designated times introduces a performance issue similar to that noted above with respect to changing the arbitration of refreshes. Namely, Reads and Writes do not flow at the times designated for the staggered refresh commands.
Therefore, a need exists for an enhanced mechanism for managing periodic commands to a volatile memory.